1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits have recently become larger in scale. As for the leading-edge micro-processing units (MPUs), a semiconductor chip including as many as one giga transistors has been developed. In a so-called planar transistor according to the related art, an n-well region that forms PMOS and a p-type silicon substrate (or p-well region) that forms NMOS need to be completely isolated from each other, as described in “CMOS OP anpu kairo jitsumu sekkei no kiso,” written by Yoshizawa Hirokazu, CQ Publishing, page 23. Each of the n-well region and the p-type silicon substrate needs a body terminal for applying a potential thereto, which increases the area.
To approach this issue, a surrounding gate transistor (SGT) has been suggested in which a source, gate, and drain are disposed in the vertical direction relative to a substrate, and the gate surrounds an island-shaped semiconductor layer. A method for manufacturing the SGT, and a CMOS inverter, NAND circuit, or SRAM cell using the SGT have been disclosed in, for example, Japanese Patent No. 5130596, Japanese Patent No. 5031809, Japanese Patent No. 4756221, and International Publication WO2009/096465.
FIG. 17 is a circuit diagram of an inverter using SGTs, and FIGS. 18A and 18B are layout diagrams of the inverter.
FIG. 17 is a circuit diagram of the inverter. Qp denotes a p-channel MOS transistor (hereinafter referred to as a PMOS transistor), Qn denotes an n-channel MOS transistor (hereinafter referred to as an NMOS transistor), IN denotes an input signal, OUT denotes an output signal, Vcc denotes a power supply voltage, and Vss denotes a reference voltage.
FIG. 18A illustrates, as an example, a plan view of the layout of the inverter illustrated in FIG. 17 including SGTs. FIG. 18B illustrates a cross-sectional view taken along a cut line A-A′ in the plan view in FIG. 18A.
Referring to FIGS. 18A and 18B, planar silicon layers 2p and 2n are disposed on an insulating film, such as a buried oxide (BOX) layer disposed on a substrate. The planar silicon layers 2p and 2n are formed of a p+ diffusion layer and an n+ diffusion layer, respectively, through impurity implantation or the like. 3 denotes a silicide layer disposed on surfaces of the planar silicon layers 2p and 2n, which connects the planar silicon layers 2p and 2n to each other. 4n denotes an n-type silicon pillar; 4p denotes a p-type silicon pillar; 5 denotes a gate insulating film surrounding the n-type silicon pillar 4n and the p-type silicon pillar 4p; 6 denotes a gate electrode; and 6a denotes a gate line. A p+ diffusion layer 7p and an n+ diffusion layer 7n are formed at the tops of the n-type silicon pillar 4n and the p-type silicon pillar 4p, respectively, through impurity implantation or the like. 8 denotes a silicon nitride film for protecting the gate insulating film 5 and so forth; 9p and 9n denote silicide layers connected to the p+ diffusion layer 7p and the n+ diffusion layer 7n, respectively; 10p and 10n denote contacts that connect the silicide layers 9p and 9n to metal lines 13a and 13b; and 11 denotes a contact that connects the gate line 6a and a metal line 13c to each other.
The n-type silicon pillar 4n, the planar silicon layer 2p, the p+ diffusion layer 7p, the gate insulating film 5, and the gate electrode 6 constitute the PMOS transistor Qp. The p-type silicon pillar 4p, the planar silicon layer 2n, the n+ diffusion layer 7n, the gate insulating film 5, and the gate electrode 6 constitute the NMOS transistor Qn. The p+ diffusion layer 7p and the n+ diffusion layer 7n serve as a source, and the planar silicon layers 2p and 2n serve as a drain. The power supply voltage Vcc is supplied to the metal line 13a, the reference voltage Vss is supplied to the metal line 13b, and the input signal IN is connected to the metal line 13c. The silicide layer 3 that connects the planar silicon layer 2p of the PMOS transistor Qp and the planar silicon layer 2n of the NMOS transistor Qn corresponds to the output OUT.
In the inverter using SGTs illustrated in FIGS. 17, 18A, and 18B, the PMOS transistor and the NMOS transistor are completely isolated from each other in the structure, and thus well isolation is not necessary unlike in a planar transistor. Further, the silicon pillars serve as floating bodies, and thus a body terminal for supplying a potential to the wells is not necessary unlike in a planar transistor. Accordingly, a very compact layout (arrangement) is realized.
As described above, the greatest feature of an SGT is that, in terms of a structural principle, a lower line formed of a silicide layer existing on a substrate side relative to a silicon pillar and an upper line connected to a contact at an upper portion of the silicon pillar can be used.